We’re looking for a RTL Engineer to design and implement key compute, memory, and interconnect components for our custom AI accelerator. You’ll work closely with architecture, verification, physical design, and ML engineers to translate AI workloads into efficient hardware structures. This is a hands-on design role with significant ownership across definition, modeling, and implementation.

This role is based in San Francisco, CA. We use a hybrid work model of 3 days in the office per week and offer relocation assistance to new employees.

Produce clean, production-quality microarchitecture and RTL for major accelerator subsystems

Contribute to architectural studies including performance modeling and feasibility analysis.

Collaborate with software, simulator, and compiler teams to ensure hardware/software co-design and workload fit.

Partner with DV and PD to ensure functional correctness, timing closure, area/power targets, and clean integration.

Build and review performance and functional models to validate design intent.

Participate in design reviews, documentation, and bring-up support across the full silicon lifecycle.

You Might Thrive In This Role If You Have:

Graduate-level research or industry experience in computer architecture, AI/ML hardware–software co-design, including workload analysis, dataflow mapping, or accelerator algorithm optimization.

Expertise writing production-quality RTL in Verilog/SystemVerilog, with a track record of delivering complex blocks to tape-out.

Experience developing hardware design models or architectural simulators, ideally for AI/ML or high-performance compute systems.

RTL & Co-design Engineer (junior)

Responsibilities

Qualification

Required

Benefits

Company

Openai

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